With the increasing down-scaling of semiconductor devices, various processing techniques, such as, photolithography are adapted to allow for the manufacture of devices with increasingly smaller dimensions. However, as semiconductor processes require smaller process windows, the manufacture of these devices have approached and even surpassed the theoretical limits of photolithography equipment. As semiconductor devices continue to shrink, the spacing desired between elements (i.e., the pitch) of a device is less than the pitch that can be manufactured using traditional optical masks and photolithography equipment.
One approach used to achieve the higher resolutions to manufacture, for example, 40 nm or smaller devices, is to use multiple pattern lithography. For example, a “half pitch” (half of the minimum photolithographic pitch achievable in a traditional photolithography system) can be achieved by forming dummy lines (e.g., at a minimum available pitch), forming sidewall aligned spacers on the dummy lines, removing the dummy lines while leaving the spacers, and then using the spacers as patterning masks to transfer the desired pattern to underlying layers. In this manner, line spacing at approximately half the minimum pitch can be achieved.
The disposition of additional materials (e.g., reverse material layers) for additional lithography patterning and cutting may be performed on the spacers prior to the removal of the dummy lines. This additional patterning/cutting allows for greater variation and/or more complex patterns to be formed in semiconductors for back end of line (BEOL) processes with small pitches. However, traditional techniques for additional patterning/cutting rely on multiple planarization steps, which increase the achievable process window and increase manufacturing cost.